In today's rapidly advancing world of semiconductor manufacturing, integration levels are increasing, device features are becoming smaller and greater demands are being made for improved device performance. As CMOS, complementary metal oxide semiconductor, devices are scaled to smaller sizes for future technologies, new materials and concepts are necessary to meet the advanced performance requirements.
CMOS technology includes NMOS (N-type metal oxide semiconductor) and PMOS (P-type metal oxide semiconductor) devices formed on the same substrate and in the same die. A critical aspect of high performance in NMOS and PMOS and various other devices is device speed. For devices to operate at high speeds, it is necessary to have a very low resistance, including a very low contact resistance between metal interconnect structures and the NMOS and PMOS transistors. Contact is made to the gate electrodes of the respective transistors as well as to both the source and drain regions of the associated transistors. One approach to provide contacts to both the source and drain regions is to form trenches penetrating through the dielectric layers above the source and drain regions and then fill the trenches with conductive materials.
During the scaling trend, various materials have been used for the gate electrode and gate dielectric for CMOS devices. One approach is to fabricate these devices with a metal material for the gate electrode and a high-k dielectric for the gate dielectric. However, high-k metal gate (HKMG) devices often require additional layers in the gate structure. For example, work function layers may be used to tune the work function values of the metal gates. Additionally, barrier (or capping) layers may assist in the HKMG manufacturing process. Although the combination of source/drain contact and HKMG formation have been satisfactory for their intended purpose, they have not been satisfactory in all respects.